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Data Sheet No. PD-6.011B 
INTERNATIONAL RECTIFIER 



HIGH VOLTAGE 



IRS11Q 



General Description 

The IR2110 is a high voltage, high speed MOS- 
gated power device driver with independent high side 
and low side referenced output channels. Proprietary 
HVIC and latch immune CMOS technologies ena- 
ble ruggedized monolithic construction. Logic inputs 
are compatible with standard CMOS outputs or with 
LSTTL outputs using pull-up resistors. Output drivers 
use low impedance totem-pole arrangement 
designed for low cross-conduction current spike. 
Propagation delays for the two channels are matched 
to simplify use in high frequency application. The 
floating channel can be used to drive a N-channel 
power MOSFET or IGBT in the high side configura- 
tion that operates off high voltage rail up to 500 volts. 

Applications 

■ High frequency switch-mode power supply 

■ DC and AC motor drives 

■ Electronic lamp ballast 

■ Battery charger 

■ Induction heating and welding 

■ Switching amplifier 



Features 

■ Floating supply designed for bootstrap operation 

— Operating offset range from - 4 to +500V 

— dv/dt immunity rated at ±50V/ns 

— Quiescent power dissipation of 1.6mW at 15V 

■ Wide output operating gate drive supply range 
from 10 to 20V 

■ Separate logic supply to interface with logic signal 

— Operating supply range from 5 to 20V 

— Logic and power ground operating offset 
range from -5 to +5V 

■ CMOS Schmitt-triggered inputs with hysteresis 
and pull-down 

■ Cycle by cycle edge-triggered shutdown logic 

■ Undervoltage lockout with hysteresis for both 
channels 

■ Output totem-pole driver designed to drive 
MOS-gated power devices 

— Peak current capability at 2A minimum 

— Switching time of 25ns typical into 1000pf 
load 

■ Matched propagation delay time for both 
channels 

— Typical 120ns turn-on delay and 94ns turn-off 
delay 

— Maximum rated matching differential of 
±10ns 

■ Latch immune CMOS. Withstand >2A reverse 
current at I/O pins 



Typical Connection 



H V 

Q 



VDDO- 

SYSTEM 
CONTROL 



CM 

DC 




° TO 
i—O LOAD 



VCC 




Pinout Assignment 







~n ho 


vddq: 




XI v B 


HIN QT 




XI v s 


sd QT 






LIN DE 




XI v C c 


vssDE 




XI COM 


DE 




Tl.LO 



For mechanical specifications see back page 



IR2110 



Absolute Maximum Ratings 

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. 
All voltage parameters are absolute voltages referenced to COM. 

The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still 
air conditions. 



Symbol 


Parameter 


Mill 


Max 


Units 


v B 


High Side Floating Supply Absolute Voltage 


-0.5 


Vs+20 


V 


v s 


High Side Floating Supply Offset Voltage 


— 


500 


VHO 


High Side Output Voltage 


Vs -0.5 


Vb+0.5 


vcc 


Low Side Fixed Supply Voltage 


-0.5 


20 


V|_0 


Low Side Output Voltage 


-0.5 


Vcc +0.5 


VDD 


Logic Supply Voltage 


-0.5 


Vss+20 


v S s 


Logic Supply Offset Voltage 


Vcc " 20 


Vcc +0.5 


V|N 


Logic Input Voltage (HIN, LIN & SD) 


V S S -0.5 


Vqd+05 


dV s /dt 


Allowable Offset Supply Voltage Transient (Fig. 16) 




50 


V/ns 


pd 


Package Power Dissipation @ T/\ < = 25°C (Fig. 19) 




1.6 


W 


R thJA 


Thermal Resistance, Junction to Ambient 




75 


°c/w 


T i 


Junction Temperature 


-55 


150 


°C 


T S 


Storage Temperature 


-55 


150 


T L 


Lead Temperature (Soldering, 10 seconds) 




300 



Recommended Operating Conditions 

The Input/Output Logic Timing diagram is shown in Fig. 1. For proper operation the device should be used 
within the recommended conditions. 

The Vs and Vss offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other 
bias conditions are shown in Fig. 2 and 3. 



Symbol 


Parameter 


Min 


Max 


Units 


v B 


High Side Floating Supply Absolute Voltage 


Vs+10 


Vs+20 




vs 


High Side Floating Supply Offset Voltage 


-4 


500 




VHO 


High Side Output Voltage 


v s 


v B 




vcc 


Low Side Fixed Supply Voltage 


10 


20 


V 


v L o 


Low Side Output Voltage 





vcc 




v D d 


Logic Supply Vcltage 


Vss +5 


Vss+20 




vss 


Logic Supply Offset Voltage 


-5 


5 




V|N 


Logic Input Voltage (HIN, LIN & SD) 


vss 


VDD 





Dynamic Electrical Characteristics 

V BIAS ( V CC. V BS> V DD) = 15V and Vss = COM unless otherwise specified. 

The dynamic electrical characteristics are measured using the test circuit as shown in Fig. 11. 







= 25°C 


Ti = -55 to 
150°C 




Symbol 


Parameter 


Min 


Typ 


Max 


Min 


Max 


Units 


Test Conditions 


Reference 


l on 


Turn-On Propagation Delay 




120 


150 




260 




Vs = OV 


Fig. 12 


toff 


Turn-Off Propagation Delay 




94 


125 




220 




Vs = 500V 




tsd 


Shutdown Propagation Delay 




110 


140 




235 




V S = 500V 




tr 


Turn-On Rise Time 




25 


35 




50 




C L = 1000pf 


Fig. 13 


tf 


Turn-Off Fall Time 




17 


25 




40 


ns 


C L = 1000pf 




Mt n 


Delay Matching, HS and LS Turn-On 






10 








1 Ht on- Lt on 1 


Fig. 14 


Mt ff 


Delay Matching, HS and LS Turn-Off 






10 








|Ht ff-Lt ff| 




DHt on 


Deadtime, LS Turn-Off to HS Turn-On 


16 


26 


36 








(Hton-Ltoff) 


Fig. 15 


DLton 


Deadtime, HS Turn-Off to LS Turn-On 


16 


26 


36 








(Lton-Htoff) 





IR2110 



Static Electrical Characteristics 

VBIAS ( v CC> v BS- v DD) = 15V unless otherwise specified. 

The V|N, Vjh and I|n parameters are referenced to Vss and are applicable to all three logic Input Pins: HIN, LIN and SD. 
The VO and IO parameters are referenced to COM or Vs and are applicable to the respective Output Pins: HO or LO. 





Tj = 25°C 


Tj = -55 to 
150°C 




Symbol 


Parameter 


Min 


Typ 


Max 


Min 


Max 


Units 


Test Conditions 


Reference 


V|H 


Logic "1" Input Voltage 


3.1 




_ 


3.3 


_ 


V 


V DD = 5V 


Fig. 4 


6.4 


_ 


_ 


6.8 





V D D = 10V 


9.5 


_ 


_ 


10 





V DD = 15V 


12.6 






13.3 




V DD = 20V 


V|L 


Logic "0" Input Voltage 






1.8 




1.7 


V D D = 5V 




_ 


3.8 


_ 


3.6 


V D D = 10V 


_ 




6 


_ 


5.7 




V D D = 15V 


— 




8.3 


— 


7.9 




V D D = 20V 


v OH 


High Level Uutput Voltage, Vbias - \/U 




U.7 


■i O 




1.5 


V 


V IN = v ih. lO = 0A 


Fig. 10 


vol 


Low Level Output Voltage, VO 


— 




0.1 


— 


0.1 


V|N = V| L , lo = OA 


ilk 


Offset Supply Leakage Current 






50 




250 


1* 


V B = V S = 500V 


Fig. 5 


'QBS 


Quiescent Vbs Supply Current 




125 


230 




500 


V|N = V|H or V| L 


Fig. 6 


'qcc 


Quiescent Vqc Supply Current 


— 


180 


340 


— 


600 


V|N = V|H or V| L 


Fig. 7 


Iqdd 


uu'coOcnt "DD ouppiy ountsiu 






ou 




fin 


Vim — V/iu nr Vn 

V IN - V IH or V IL 




l|N + 


Logic "1" Input Bias Current 


— 


15 


30 


— 


70 


V| N = 15V 


Fig. 8 


l|N~ 


Logic "0" Input Bias Current 






1 




10 


V| N = 0V 




VBSUV+ 


V BS Supply Undervoltage Positive 
Going Threshold 


7.7 


8.7 


9.7 







V 




Fig. 9 


Vbsuv- 


Vbs Supply Undervoltage Negative 
Going Threshold 


7.3 


8.3 


9.3 








V CCUV+ 


V CC Supply Undervoltage Positive 
Going Threshold 


7.6 


8.6 


9.6 








vccuv- 


Vqc Supply Undervoltage Negative 
Going Threshold 


7.2 


8.2 


9.2 








io+ 


Output High Short Circuit Pulsed 
Current 


2 










A 


VOUT = 0V V| N = 15V, 
PW < = 10 




"o- 


Output Low Short Circuit Pulsed 
Current 


2 










V UT = 15V V| N = 0V, 
PW <= 10 M s 





Functional Block Diagram 




HV 
LEVEL 
SHIFT 



PULSE 
GEN 




-f 















v D0' v CC 


o— 


LEVEL 




SHIFT 




COM 



IR2110 

Typical 



nee 



HIN 
LIN 

SD 

HO 
LO 



J 



Jl 



J 



Fig. 1 — Input/Output Timing Diagram 



it 

o 10 



VDD 


- V S S = 5 


TO 20V, 


I 

T A = 25°C 











































































10 12 14 16 18 20 

V CC , FIXED SUPPLY VOLTAGE 

Fig. 3 — Maximum V ss Positive Offset 
Voltage vs. V cc Supply Voltage 



— 10 



2 




0.001 



-60 -30 30 60 90 120 150 
Tj. TEMPERATURE (°C) 



Fig. 5 — Offset Supply 
Current vs. Temperature 



-2 



=> 

CO 

t— 

te -6 















vcc 


= 10 TO 2 


DV T A = 


= 25°C 











































10 12 14 16 18 

V BS , FLOATING SUPPLY VOLTAGE (V) 

Fig. 2 — Maximum Vg Negative 
Offset vs. Vgg Supply Voltage 



- 10 



+ 



o 

>-. 



300 



250 



200 



•& 150 



5 100 



50 



20 





= -'- 


5°C T 


D 150* 


C 


































\ 


TH+ 




/v T 


H" 



























































2 4 6 8 10 12 14 16 18 20 
V DD , LOGIC SUPPLY VOLTAGE (V) 

Fig. 4 — Input Logic Threshold 
vs. V DD Supply Voltage 



v B s 


I 

= 10V, 15V & 
LOGIC "1" AND 


20V, NC 
LOGIC 1 


LOAD 

0" 








20V 


3BS1 






20VIq E 


ISO 


















15VI 


3BS1 






15VI QE 


SO 




10VI 


3BS1 






FioVlQB 


SO 













-60 -30 30 60 90 120 150 
Tj, TEMPERATURE (°C) 

Fig. 6 — Quiescent V QS Supply 
Current vs. Temperature 



Typical Performance Characteristics 



IR2110 




30 60 90 120 
Tj, TEMPERATURE (°C) 



40 

35 

Ji 

£ 30 

uj 

cc 
cc 

S 25 

i 

m 

^ 20 

Q- 

r 15 

o 
to 

3 10 
+ 

5 


























V|N = 


20V, 














I0V 




























10V, 














-5V— 































Fig. 7 — Quiescent Vqq Supply 
Current vs. Temperature 



-60 -30 30 60 90 120 150 
Tj, TEMPERATURE (°C) 

Fig. 8 — Logic "1" Input Bias 
Current vs. Temperature 



9.2 



i— 

O 



+ 

:> 



86 



8.4 



8.2 



8 

-60 























V BSUV 




CCUV+ 












-^v 








VBS 






CUV" 































-30 30 60 90 
Tj, TEMPERATURE (°C) 



120 150 



Fig. 9 — Undervoltage Lockout 
vs. Temperature 



S 3.75 



05 3.5 



y 3.25 



23 

tS? 2.75 



2.5 





\ 


C = V B£ 


= V BIA 


i T A = 


= 25°C 































































5 10 15 

V BIAS, SUPPLY VOLTAGE (V) 

Fig. 10 — Output Device On 
Resistance vs. Supply Voltage 



20 



VfJC = 15V 
o 




500V) 




Fig. 11a 



— Switching Time Test Circuit 



Fig. 11b — Switching Time 



Waveform Definition 



IR2110 

Typical Performance Characteristics 



180 



160 



140 



2 120 



100 



60 



C L = 


I 

1000 pF. \ 


CC = ^BS 
T A = 25°( 


= v DD = 


1 

15V, 




























Ht on 












^Ltoff 













20 



Fig. 



10 12 14 16 18 

V SUPPLY. SUPPLY VOLTAGE (V) 

12a — Delay Time vs. Supply Voltage 





135 




130 




125 


UJ 




y— 


120 






_! 




UJ 
Q 


115 


LU 

D 




CO 




m 


110 


CD 


m 




3= 
_p 


105 


in 




o 


100 




95 




90 







'BS = 


^CC = 


VDD = 


15V, C 


= 10( 


pF, 


1 








T A = i 


5°C 






























H, on" 
































4- 




































Htoff 





















-10 10 20 30 40 50 60 
V S , OFFSET VOLTAGE, (V) 

Fig. 12c — High Side Delay 
Time vs. V g Offset Voltage 



40 



35 



30 



25 



20 



10 





vcc 


= VBS 


= 15V, 


C L = 1 


)00 pF 






















V 




























tf 

























-60 



-30 



30 60 90 120 150 
Tj, TEMPERATURE (°C) 

Fig. 13b — Rise and Fall Time vs. 
Temperature 



200 
180 
160 
140 



§ 120 



J? 100 



60 



v cc 


= V BS 


= V DD 


— 15V, 


c L = 


000 pF 














Ht on . 






























Lt off 



























































-60 -30 30 60 90 120 150 
Tj, TEMPERATURE (°C) 

Fig. 12b — Delay Time vs. Temperature 





30 




28 




26 


"35* 
cz 


24 


LU 




I— 


22 


_J 




_l 
<£ 

Q 


20 






LU 

HO 


18 


CC 




i 


16 




14 




12 




10 





I 

= 1000 pF, V CC = V E 


s = 10 TC 


20V. 




>t 


— U 




















































tf 



































10 12 14 16 18 

V SUPPLY. SUPPLY VOLTAGE (V) 

Fig. 13a — Rise and Fall 
Time vs. Supply Voltage 



20 



Q 

uj 
CO 
CC 




1000 

C L . LOAD CAPACITANCE, (pF) 

Fig. 13c — Rise Time/Fall 
Time vs. Load Capacitance 



10000 



Typical Performance Characteristics 



HIN 
LIN 



50% 




V S = 500V 



TYPICAL Mt on = Mt off = ns 

Fig. 14 — Delay Matching 
Waveform Definitions 



V CC = 15V 
o 



J_10 J_ 1 

J>f T>' f 



HV = TO 500V 
p 



10KF6 



9 3 6 

5 
7 



11 IR2110 

12 



2 u°t -mo T 100 " F 



-OHO 



OUTPUT 
MONITOR 



10 
KF6 



IRF ( +| 

820 



1 



> 50 V/ns 



_TL 



Fig. 16 — Floating Supply Voltage 
Transient Test Circuit 



IR2110 



LIN 



HIN 



50% 



50% 



LO 


90%^ 


HO 







v s = ov 




V S = 500V 



TYPICAL DHt 
Fig. 15 — Deadtime Waveform Definitions 




0.001 



V BIAS= 15V ' C L = 1000 PF AND T A = 25°C 
I I I I I I I I I i I I i 



10K 100K 1 MEG 

f, SWITCHING FREQUENCY (Hz) 

Fig. 17a — High Voltage Power 
Dissipation vs. Switching Frequency 




_L 10 J_ .1 



f = 10 kHz 4- 
TO 

1 MHz 
PW = 50% 



10 



11 
12 



13 





^7 



0.1 

: M F 



10 

>F (±)15V 



10 



flHV 

(±) HV = TO 500V 



=p C L = 1000 pF ± 



HVPD = (HV • l HV )/2 
OR P D PER LEVEL SHIFT EVENT 



Fig. 17b — High Voltage Power Dissipation Test Circuit 



IR2110 

Typical Performance Characteristics 



10 



o 



g 0.1 

LU 
CD 

§ 

I 0.01 




0.001 



VCC = V B S = V DD = 15V 
T A = 25°C 

UiliJ i i i Him l 



10K 100K 1 MEG 

f. SWITCHING FREQUENCY (Hz) 



10 MEG 



Fig. 18a — Low Voltage Power 
Dissipation vs. Switching Frequency 



1.8 
1.6 

E 1.4 

z 

o 

I 12 

CO 
CO 

LU 

£ 0.8 
s 

:=> 

I 0.6 
1 

£> 0.4 
0.2 


















R thjA 


= 75°C/ 


* T j( 


nax - 1! 


>0°C 























































































25 50 75 100 125 150 
T A . AMBIENT TEMPERATURE (°C) 



175 



Fig. 19 — Maximum Power 
Dissipation vs. Ambient Temperature 



Jin @_ 



f = 10 kHz 
TO 

10 MHz 
PW = 50% 



10 



13 



]_ 0.1 ]_ 10 



t 'LV 

(±) VBIAS 
J (= 15V) 



C L (= TO 10,000 pF) 



LVPD = V B |AS ■ ILV 



Fig. 18b. — Low Voltage Power 
Dissipation Test Circuit 



HEXFET 
SIZE 


TYPICAL 

k 


TYPICAL 
tf 


2 


25 ns 


17 ns 


3 


38 ns 


23 ns 


4 


53 ns 


34 ns 


5 


78 ns 


54 ns 


6 


116 ns 


74 ns 



Fig. 20 — HEXFET Die Size vs 
Time (VbiaS = 15V) 



HEXFET 
TYPE 


HV= 
100V 


200V 


300V 


400V 


820 


2000 


1200 


700 


350 


830 


1600 


1100 


640 


330 


840 


1100 


820 


540 


300 


P450 


640 


540 


400 


250 


P460 


490 


460 


340 


230 



T A = 25°C AND 
V B IAS = 15V 



Fig. 21 — Maximum Switching Frequency, f m ax (kHz) 

(f max = switching frequency at which Tj = Tj max and is derived from calculation 
using typical electrical and thermal ratings. For operation at higher Ta, fmax should 
be derated accordingly.) 



IR2110 



Functional Description 

The IR2110 is a monolithic high voltage, high speed 
two channel power MOSFET or IGBT driver. Refer to 
the section on Functional Block Diagram for the internal 
partitioning of the various circuit blocks. The driver 
translates logic input signals into corresponding "in- 
phase" low impedance outputs. The low side channel 
output (LO) is referenced to a fixed rail (Vcc) and the 
high side channel output (HO) is referenced to a floating 
rail (Vbs) with offset capability up to 500V. 

The logic circuit provides the control pulses for the 
two output channels corresponding to the logic inputs 
as indicated by the Input/Output Timing Diagram in 
Fig. 1. The HO and LO outputs are in phase with the 
HIN and LIN logic inputs. The two outputs will turn off 
when the SD input switches high and the outputs will 
remain off even after the SD input returns to low until 
the next rising edge of the respective inputs. In the case 
when Vcc ' s below the undervoltage trip point the UV 
detect circuit will send a shutdown signal to disable both 
channels. Also a separate UV detect block is used to 
disable the high side channel when Vbs is below its 
own undervoltage trip point. The logic inputs use 
Schmitt trigger circuits with a hysteretic band of 
0.1 * Vqd to provide high noise immunity and can accept 
inputs with slow rise time. The logic circuit is referenced 
to its own logic supply to allow the use of a lower supply 
voltage than the output operating supply voltage. A high 
noise immunity Vqd/VCC level-shifting circuit is used 
to translate logic signal to the output drivers. With a 
+5V rated offset capability between the logic ground 
(Vss) and power ground (COM), the logic circuit is 
unaffected by the noise coupling generated by the 
switching action of the output drivers. 

Propagation delay for the two channels are matched 
using the low side delay circuit to simplify the timing 
requirements of the control pulses. The turn-on delay 
is matched at 120ns for the low side channel (Lt n) and 
the high side channel (Ht n) with Vs at 0V since the 
high side turn-on command is usually executed when 
Vs is at or near OV The turn-off delay is matched at 
94ns for the low side channel (Lt ff) and the high side 
channel (Ht ff) with Vs at 500V since the high side turn- 
off command is usually executed after the high side 
power MOSFET is "on" and Vs is at or near the high 
voltage rail. 

Both channels use identical low cross-conduction 
totem pole output connected transistors. The output 
driver consists of two N-channel MOSFETs with peak 
current capability above 2A and on resistance of less 
than 3 ohms (Fig. 10). One output MOSFET is 
connected as a source follower and the other in 
common source configuration. Because of the totem 
pole arrangement the rise time is slower than the fall 
time driving capacitive load. For a typical 3300pf load 
the rise and fall times are 50ns and 33ns respectively. 

For the high side channel, narrow "On" and "Off" 
pulses triggered respectively by the rising and the 
falling edge of HIN are generated by the pulse 
generator. The respective pulses are used to drive 
separate high voltage DMOS level translators that set 
or reset a RS latch operating off the floating rail. Level 
shifting of the ground referenced HIN signal is thus 
accomplished by transposing the signal references to 
the floating rail. Because each high voltage DMOS level 



translator is turned on for only the duration of the short 
"On" or "Off" pulses with each set or reset event, power 
dissipation is minimized. False triggering of the RS latch 
from fast dv/dt transients on the Vs node is effectively 
differentiated from normal pull-down pulses through a 
pulse discriminator circuit such that the high side 
channel is essentially immune to any magnitude of dv/dt 
value. Also the high voltage level shifting circuit is 
designed to function normally even when the Vs node 
swings more than 4V below the COM pin. This condition 
can often occur during the recirculation period of the 
output free-wheeling diode. 

Application Guidelines 

(Also see Application Note AN-978A for details) 

The IR2110 is typically used to drive two high voltage 
N-channel power MOSFETs or IGBTs configured in half- 
bridge, dual-forward or other topologies. The fixed rail 
referenced output is used to drive a low side connected 
power MOSFET. The floating output channel is used 
to drive a power MOSFET in the high side configuration 
that requires an over-rail gate drive. Refer to the section 
on Typical Applications for the various circuit topologies 
where the IR2110 is applicable. 

Typically, the floating supply is derived from the fixed 
supply using a bootstrap technique as shown in the 
section on Typical Connection. The charging diode must 
have a voltage withstand capability higher than the peak 
HV bus voltage. To minimize power dissipation a fast 
recovery diode is recommended. The value of the 
bootstrap capacitor depends on the switching 
frequency, duty cycle and gate charge requirement of 
the power MOSFET. The voltage across the capacitor 
should not be allowed to drop below the under-voltage 
lockout threshold, otherwise protective shutdown will 
occur. A 0.1 fJF capacitor is usually suitable for 
applications switching above 5 KHz. 

Supply bypass capacitors between Vcc and COM 
and between Vqd and Vss are required to supply the 
transient current needed for switching the capacitive 
loads. These capacitors, together with the reservoir 
capacitor across Vb and Vs, must be connected close 
to the device. A 0.1 yF ceramic disk capacitor in parallel 
with a 1 fjF tantalum capacitor is recommended for Vcc 
bypass. A 0.1 ^F ceramic disk capacitor is usually 
adequate for the logic supply. 

The outputs of the IR2110 are designed to deliver gate 
drives for fast switching speed even for high current 
power MOSFETs with relatively high gate charge 
requirement. The typical switching speed for various 
standard power MOSFET sizes is shown in Fig. 20. To 
minimize inductance in the gate drive loop, each 
MOSFET should have its own dedicated connection 
going to Pin 2 and 5 of the IR2110 for the return of the 
gate drive signal. For smaller power MOSFETs a series 
gate resistor for each output is recommended to limit 
switching speed. The value of the gate resistor depends 
on EMI requirement, switching losses and the 
maximum allowable dv/dt. 

The total power dissipation of the IR2110 is a function 
of HV bus voltage, Vcc and Vdd voltages, switching 
frequency, duty cycle, delivered gate drives charge, and 
operating junction temperature. The total dissipation 
can be divided into two categories: High voltage and 
low voltage switching. 



IR2110 



The high voltage dissipation can be calculated by the 
following formula: 

PD(HV) = HVHlk* d + (V B on+VBoff)*QP*f 
> , ' v , . 

static dynamic 

with HV the high voltage bus voltage, l|_K the leakage 
current of Vb to ground, d the duty cycle of the high 
side switch, Qp the pulsed charge of high voltage level 
shifter, VBon the average voltage of Vb during the turn- 
on pulse, VBoff the average voltage of Vb during the 
turn-off pulse and f the switching frequency of the high 
side channel. The level shifting losses are usually much 
larger than the leakage losses such that the static term 
can be neglected for most applications. Fig. 17 shows 
the total high voltage dissipation as a function of 
switching frequency at various fixed Vs voltage level. 
Note that the graph only shows the high voltage power 
dissipation per set or reset event at the particular fixed 



Vs level. Keep in mind that in actual application Vs is 
swinging during the level shifting event. 

The low voltage dissipation can be calculated by the 
following formula: 

PD(LV) = Vbias'lQtot + 2*Vbias*Qg*f + Vbias*Qcmos*f 
, < ^_ , 1 

static dynamic 

with Vbias the low voltage bias voltage assuming Vqd 
= Vcc = V BS. 'Qtot the total quiescent current, Qg 
the delivered gate charge per driven MOSFET, f the 
switching frequency and Q C mos the switching losses 
associated with the internal CMOS circuitry. The 
quiescent losses are usually much smaller than the 
dynamic losses such that the static term can be 
neglected. Fig. 18 shows the total low voltage power 
dissipation as a function of switching frequency at 
various load conditions. The switching losses 
associated with internal circuitry (Qcmos) are shown in 
the graph for the case of "0 pf" loading condition. 



Typical Applications 



+15Vo- 



1 mf =s= 



10KF6 
-tt- 



<j> Vr < 500V 



n_n_ 



IR2110 

10 
11 



I— P2 2\— i 

13 



=4=0.1 




LOAD 



LOGIC GND POWER GND 

Buck Converter 



+15Vo- 




oV R < 500V 



0.1 y!F 4= 



LOGIC GROUND POWER GROUND 

Dual Forward Converter 



IR2110 

Typical Applications Continued 

+15V 




3-Phase Bridge Motor Drive 



+15V 



I 



0.1 yf =t 







6 


9 




7 








5 


10 


IR21- 


3 


12 
11 




1 


13 




2 





10KF6 
0.1 m f 



4=1 



i 





V R < 500V 

_ U 



CURRENT 
SENSING 



V 





+15V 



10KF6 



0.1 /iFy 



1 M F 



i 



6 






7 




9 




5 


<= 




3 


IR21 


10 


1 




12 




11 


2 




13 





d= 0.1 M F 



H-Bridge 

Typical implementation of an H-bridge with cycle-by-cycle current mode control 



IR2110 

Mechanical Specification 



1 270 [0.050) 



1 168 (0 046) 



1 270 (0 0501 
1 168 ( 046) 




y y y y y y y 



6 350 (0.250) 7 671 (0.302) 



6.248 (0 246) 7 569 (0.298) 




2 032 [ 080) 
"l 930 (0.076) 



3.480 (0.137) f / 
3 378(0 133)1 \ " 



3' 



508 (0 0201 



0.406 (0.016) 



2.591 (0.102) 
2.489 (0 098) 
19 253 (0 758) 



1 753 (0.069) 



1 651 (0.065) 



17^ 



1 575 [0 062) 



1 473 (0.058) 



19.151 (0.754) 



14 Pin Dip Package 



International 
SRectjfier 

WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245. Tel: (213) 772-2000, Twx: 4720403 
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB England, Tel: (0883) 713215, Twx: 95219 

IR CANADA: 101 Bentley St., Markham, Ontario L3R 3L1. Tel: (416) 475-1897 IR GERMANY: Saalburgstrasse 157, D-6380 Bad Homburg, Tel: 6172-37066. IR ITALY: Via Liguria 49 
10071 Borgaro, Torino, Tel: (011) 470 1484. IR FAR EAST: K&H Building, 30-4 Nishiikebukuro 3-Chrome. Toshima-ku, Tokyo 171 Japan, Tel: (03) 983 0641. IR SOUTHEAST ASIA: 
190 Middle Road, HEX 10-01 Fortune Centre, Singapore 0718. Tel: (65) 336 3922. 

Sales Offices, Agents and Distributors in Major Cities Throughout the World. 
Printed in the USA 12/90 Data and specifications sub/act n change wmout notice. (1088) 



Data Sheet No. PD-6.016 
INTERNATIONAL RECTIFIER 



IOR 



HIGH VOLTAGE 
MOS GATE DRIVER 



General Description 

The IR2110S is the SOIC or small outline IC form of the IR2110; a high voltage, high speed MOS- 
gated power device driver with independent high side and low side referenced channels. Refer to 
Data Sheet No. PD-6.011B for electrical parameters. This surface mounted device is particularly 
well suited for applications that require high density circuit layout. 

With the exception of the maximum thermal resistance and maximum power dissipation all of 
the device characteristics specified on the IR2110 plastic dip package apply to the IR2110S. As with 
the IR2110 plastic dip the IR2110S has a maximum operating temperature range from -55°C to 150°C. 



Absolute Maximum Ratings 

Symbol Parameter Max Units 

Pq Package Power Dissipation @ Ta < = 25C, Fig. 1 1.25 W 

R thJa Thermal Resistance, Junction to Ambient 100 °C/W 



v ddo- 

SYSTEM 
CONTROL 



Typical Connection 



11 




8 

7 


12 


o 


6 




13 


T— 




14 


CM 


3 


DC 


15 




2 
1 









-r 6 



TO 



Pinout Assignment 



NC 
NC 

VDD 
HIN 
SD 
LIN 

v S s 

NC 



c/> 



CM 



H o 



NC 
NC 

V C C 
COM 

L0 



FOR MECHANICAL SPECIFICATIONS SEE BACK PAGE 



IR2110S 




HHHRRRRR 




mrnn 



7.08 (0.303) 
7.2© <0.207) 



MOTES: 

1 DIMENSIONING AND TOLERANCING F* E R ANSI Y 1 <t SM 1 0O2 

£^ THIS DIMENSION IS THE LENGTH OF TERMINAL FOR 
SOLDERING TO THE SUBSTRATE 

3 ALL DIMENSIONS ARE SHOW N IN MILLIMETERS (INCHES) 



-1 O 46 <0.-*-l 2) 



"1 O . 1 i (0 .3OC 










tin 


1TH 


y 





3Q (O OI g) 1* 
. 1 O (0.007) ' 




o.-*s (O.oi a> 

0_30 (OOI -4 ) 
|^|p.-|2 (O.OOS) (g)| 



1 O SO (Q.421 ) 
6.8<<* (0.30 1 ) 



0.43 (OOI 7) 
O.^ 1 (O OOf») 



K ^ -i (0 0-41 ) 

\ I I O SO (0.023) 



T 



2.5-» (O. t OO) 
2 (O.OS4) 



0.-*3 (O .O 1 7) 

o -i e ( o ooo) 



1 27 (O.OSO) 



International 
S Rectifier 

WORLD HEADQUARTERS: 233 Kansas St.. El Segundo. California 90245. Tel: (213) 772 2000. Twx 4720403 
EUROPEAN HEADQUARTERS: Hurst Green, Oxted. Surrey RH8 9BB England. Tel: (0883) 713215. Twx: 95219 

IR CANADA: 101 Benlley SI . Markham. Ontario L3R 3L1 Tel: (416) 475-1897 IR GERMANY: Saalburgstrasse 157. D-6380 Bad Homburg, Tel: 6172-37066. IR ITALY: Via Liquna 49 
10071 Borgaro. Torino. Tel: (011) 470 1484 IR FAR EAST: K&H Building, 30-4 Nishukebukuro 3-Chrome. Toshima-ku. Tokyo 171 Japan. Tel: (03) 983 0641. IR SOUTHEAST ASIA: 

190 Middle Road. HEX 10-01 Fortune Centre. Singapore 0718, Tel: (65) 336 3922 

Sales Oflices, Agents and Distributors in Major Cities Throughout the World. 



Printed in the USA 8/90 



Data and specifications sub/ect to change without notice 



1 1088) 



Data Sheet No. PD-6.014 



INTERNATIONAL- RECTIFIER 



HIGH VOLTAGE 
MOS GATE DRIVER 



IRS11QC 



General Description 

The IR2110C is the die form of the IR2110 (refer to Data Sheet No. PD-6.011B); a high voltage, high speed 
MOS-gated power device driver with independent high side and low side referenced channels. The IR2110C 
is ideal for use in power hybrid modules where substantial savings in weight and volume can be obtained. 

Some of the device characteristics specified on the packaged device are packaging dependent and there- 
fore limits cannot be guaranteed in die form. These are: 



Pq max. 
RthJA max. 
Iq± min. 



Maximum power dissipation 
Maximum thermal resistance 
Minimum short circuit current 

and dynamic electrical characteristics 

Maximum propagation delays 
Maximum rise and fall times 
Maximum delay matching 
Maximum and minimum deadtimes. 

All typical performance characteristics of the IR2110 apply to the IR2110C, however, final package perfor- 
mance is dependent upon the user's assembly techniques. 



Mechanical Specifications 

Front Metal 
Back Metal 
Die Thickness 



aluminum Wo silicon 
chromium-nickel-silver 
16 ± 1 mils 



Typical Connection 



HV 

Q 



Vddo- 

SYSTEM 
CONTROL 



o 

o 




3 TO 
I— O LOAD 



6 

vcc 




Die Connection — Refer to Diagram on Reverse Side 



IR2110C 



3E DRIVER 

0.100 ± 0.006 




0.117 ±0.008 



LEGEND 

DIMENSIONS IN INCHES 



PAD # 


FUNCTION 


DIMENSIONS 
HxW 


DATUM 

X Y 


1 


vss 


0.0069 x 0.0049 


0.0000, 0.0000 


2 


LIN 


0.0049 x 0.0049 


0.0019, 0.0307 


3 


SD 


0.0049 x 0.0049 


0.0019, 0.0471 


4 


HIN 


0.0049 x 0.0049 


0.0019, 0.0635 


5 


V D D 


0.0059 x 0.0059 


-0.0002, 0.0975 


6 


HO 


0.0061 x 0.0055 


0.0513, 0.0920 


7 


v B 


0.0065 x 0.0055 


0.0778, 0.0946 


8 


v S 


0.0061 x 0.0055 


0.0774, 0.0542 


9 


vcc 


0.0065 x 0.0055 


0.0804, 0.0402 


10 


COM 


0.0061 x 0.0055 


0.0800. -0.0002 


11 


LO 


0.0061 x 0.0055 


0.0539, 0.0022 


TOLERANCE 


±0.0005 


±0.0002 



International 
SRectifier 

WORLD HEADQUARTERS: 233 Kansas St., El Segundo. California 90245, Tel: (213) 772-2000, Twx: 4720403 
EUROPEAN HEADQUARTERS: Hurst Green, Oxted. Surrey RH8 9BB England, Tel: (0883) 713215, Twx: 95219 

IR CANADA: 101 Bentley St., Markham, Ontario L3R 3L1. Tel: (416) 475-1897 IR GERMANY: Saalburgstrasse 157, D-6380 Bad Homburg, Tel: 6172-37066. IR ITALY: Via Liguna 49 
10071 Borgaro. Torino. Tel: (011) 470 1484. IR FAR EAST: K&H Building, 30-4 Nishiikebukuro 3-Chrome. Toshima-ku, Tokyo 171 Japan, Tel: (03) 983 0641. IR SOUTHEAST ASIA: 
190 Middle Road, HEX 10-01 Fortune Centre. Singapore 0718, Tel: (65) 336 3922. 

Sales Offices, Agents and Distributors In Ma|or Cities Throughout the World. 
Printed in the USA 4/90 Data and specifications subtect to change without notice (1088)